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  • 标题:Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Technology
  • 本地全文:下载
  • 作者:Rajendra Prasad S ; B K Madhavi ; K Lal Kishore
  • 期刊名称:International Journal of VLSI Design & Communication Systems
  • 印刷版ISSN:0976-1527
  • 电子版ISSN:0976-1357
  • 出版年度:2011
  • 卷号:2
  • 期号:4
  • 出版社:Academy & Industry Research Collaboration Center (AIRCC)
  • 摘要:The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%
  • 关键词:SRAM Cell; CNTFET; 32nm Technology; HSPICE; Low-Power
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